Dynamic logic circuits have become prevalent in high performance integrated circuits because they offer faster switching speeds and a smaller area than static logic circuits. Dynamic logic circuits generally use complementary metal oxide semiconductor (CMOS) devices.
As depicted in FIG. 1, a dynamic logic circuit 102 includes a p-type channel MOS (PMOS) precharge transistor 104 coupled to a voltage source 106 having a voltage level (Vdd), an n-type channel MOS (NMOS) logic network 108, and an NMOS footer transistor 110 coupled to ground 112. The output is measured at a dynamic node 114. The circuit operation is controlled by a clock signal (CLK) that is applied to both the PMOS precharge transistor 104 and the NMOS footer transistor 110.
The dynamic logic circuit 102 has two phases of operation. When the clock signal is at a logic zero, the dynamic logic circuit 102 is in a precharge phase, and the dynamic node 114 is charged to Vdd. When the clock signal is at a logic one, the dynamic logic circuit 102 is in the evaluation phase, and the voltage at the dynamic node 114 depends on the inputs and the Boolean function represented by the NMOS logic network 108. If the conditions are such that the NMOS logic network 108 conducts, the dynamic node 114 discharges. However, if the NMOS logic network 108 does not conduct, the dynamic node 114 becomes a floating node and remains at Vdd.
Unfortunately, the transistor gates of dynamic logic circuits cannot be directly cascaded. Dynamic logic circuits also have problems with charge leakage and charge sharing.
Referring to FIG. 2, a domino logic circuit 202 is a type of dynamic logic that employs a dynamic part with a precharge transistor 204 coupled to a voltage source 206 having a voltage level (Vdd), an NMOS logic network 208, an NMOS footer transistor 210 coupled to ground 212, and a dynamic node 214. The dynamic part is followed by a static inverter 216. The inverter 216 enables the gates of the transistors to be directly cascaded in the domino logic circuit 202.
The domino logic circuit 202 includes a keeper transistor 218 to overcome the problems of charge leakage, charge sharing, and floating nodes. The keeper transistor 218 generally is a weak PMOS transistor used to retain the precharge state of the dynamic node 214 while awaiting operation of the NMOS logic network 208 in the evaluation phase.
During the evaluation phase, if the NMOS logic network 208 remains disabled, the dynamic node 214 retains its precharge state, and the keeper transistor 218 helps maintain the stability and robustness of the circuit. Also, CMOS domino circuits with keepers draw any static current that exists, which enables the quiescent or static current (Iddq) in the circuit to be testable. However, the keeper transistor 218 results in a performance reduction of the circuit due to the keeper transistor's added parasitic capacitance 220 at the dynamic node 214.
While testing static CMOS circuits has received a lot of attention, little attention has been paid to testing dynamic CMOS circuits. Fault modeling is used in a testing scheme to describe the behavior of the circuit under several modes of physical defects and broadly examines ways in which that circuit can fail. Accurate fault modeling of physical defects in a circuit is needed for a good testing methodology.
Testing faults in domino logic circuits is a challenge due to their susceptibility to noise and their unique circuit topology. The footer and keeper transistors in CMOS domino circuits are used to counter problems such as charge sharing and charge leakage. The footer and keeper transistors do not directly affect the logic behavior of the circuit. Therefore, tests based on purely logical fault models cannot be used to test them. This results in a large number of faults in the footer and keeper transistors that are untestable using conventional tests that are based on purely logical fault models. The lack of an acceptable fault model for domino logic circuits contributes to the complexity of testing them.
Systems and methods are needed to detect faults in domino logic circuits, including faults in the keeper and footer devices. Systems and methods are needed for detecting faults in simple and complex circuits.